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Design of adaptive communication channel buffers for lowpower area-efficient network-on-chip architecture

机译：用于低功率区域高效片上网络架构的自适应通信信道缓冲器的设计

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Avinash Kodi; Ashwini Sarathy; Ahmed Louri;
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年度 2007
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1. An Area-Efficient FPGA Implementation of Network-on-Chip (NoC) Router Architecture for Optimized Multicore-SoC Communication [J] . R. Poovendran, S. Sumathi Sensor Letters: A Journal Dedicated to all Aspects of Sensors in Science, Engineering, and Medicine . 2018,第7期

机译：用于优化多芯SOC通信的芯片上网（NOC）路由器架构的区域有效的FPGA实现
2. Self-Reconfigurable Channel Data Buffering Scheme and Circuit Design for Adaptive Flow Control in Power-Efficient Network-on-Chips [J] . Bondade R., Ma D. Circuits and Systems I: Regular Papers, IEEE Transactions on . 2010,第11期

机译：高效节能片上网络中自适应流量控制的自重配置通道数据缓冲方案和电路设计
3. PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design [J] . N. Wang, A. Sanusi, P. Y. Zhao, Journal of Signal Processing Systems . 2010,第3期

机译：PMCNOC：流水线多通道中央缓存片上网络通信架构设计
4. Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture [C] . Avinash Kodi, Ashwini Sarathy, Ahmed Louri ACM/IEEE Symposium on Architecture for networking and communications systems . 2007

机译：低功耗，面积效率低的片上网络架构的自适应通信通道缓冲器的设计
5. Architecture designs for improving performance in fading channel communications. [D] . Kuo, Wen-Yi. 1994

机译：用于提高衰落信道通信性能的体系结构设计。
6. Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things [O] . Muhammad Rashid, Naveed Khan Baloch, Muhammad Akmal Shafique, 2020

机译：容错网络上环路路由器架构在内容互联网上的异构计算系统
7. Adaptive Inter-router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architectures [O] . 2014

机译：适用于低功耗，面积有效且可靠的片上网络（NoC）架构的自适应路由器间链路
8. <learning systems, adaptive systems, signal design, and channel models for space communication - communication theory area< annual report for 1964 [R] . Hancock, J. C., et al. 1965

机译：＆lt;空间通信的学习系统，自适应系统，信号设计和信道模型 - 通信理论领域＆lt; 1964年年度报告

Design of adaptive communication channel buffers for lowpower area-efficient network-on-chip architecture

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